1. Field of the Invention
The present invention relates to a capacitor and a method for manufacturing the same.
2. Description of the Related Art
Capacitors used in semiconductor devices have either polysilicon-insulator-polysilicon (PIP) or metal-insulator-metal (MIM) structures. Since PIP capacitors may have a plan or platform shape, they generally occupy a large area, making it difficult to reduce the chip size.
A PIP capacitor according to the prior art will be described with reference to FIG. 1, which is a sectional view.
In FIG. 1, a field oxide layer 11 is formed on a silicon substrate 10 and the lower electrode 12 of the capacitor is formed on the field oxide layer 11. The lower electrode 12 is formed by depositing and patterning a polysilicon layer. Then, a dielectric layer 13 and an upper electrode 14 of the capacitor are formed on the lower electrode 12. The dielectric layer 13 and the upper electrode 14 are formed by patterning and depositing an oxide or nitride layer (e.g., SiO2 or Si3N4) and a polysilicon layer, respectively.
After an inter-layer dielectric layer is deposited on the overall structure and selectively etched, contacts 16 (which are connected to either the upper or lower electrodes 12 and 14 of the capacitor) and metal wiring 17 (connected to contact 16) are formed thereon.
As described above, because conventional PIP capacitors have a plan or platform shape, the area occupied by the capacitor on the chip is large, which is an obstacle to reduction of chip area.